`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 02/01/2021 08:51:18 PM
// Design Name: 
// Module Name: PulseGen
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module PulseGen(
input clk,
input rstn,
input gen,
output reg pulse
);

parameter idle = 2'b00;
parameter redy = 2'b01;
parameter relz = 2'b10;

reg [1:0] state, nextstate;

always@(posedge clk)
if(!rstn)
begin
    state <= idle;
end
else
begin
    state <= nextstate;
end

always@(*)
    case (state)
        idle: 
        if(gen)  nextstate = redy;
        else     nextstate = idle;
        redy:
        if(gen)  nextstate = redy;
        else     nextstate = relz;
        relz:
                 nextstate = idle;
        default: nextstate = idle;
    endcase


always@(posedge clk)
if(!rstn)
begin
    pulse <= 0;
end
else
begin
    case (state)
        idle: pulse <= 0;
        redy: pulse <= 0;
        relz: pulse <= 1;
        default: pulse <= 0;
    endcase
end

endmodule